I/O Maps
EE Map
EE Timers
- 
100000xxhTimer 0 - 
100008xxhTimer 1 - 
100010xxhTimer 2 - 
100018xxhTimer 3 
Image Processing Unit (IPU)
- 
10002000h8hIPU Command - 
10002010h4hIPU Control - 
10002020h4hIPU bit pointer control - 
10002030h8hTop of bitstream - 
10007000h10hOut FIFO (read) - 
10007010h10hIn FIFO (write) 
Graphics Interface (GIF)
- 
10003000h4hGIF_CTRL - Control register - 
10003010h4hGIF_MODE - Mode setting - 
10003020h4hGIF_STAT - Status - 
10003040h4hGIF_TAG0 - Bits 0-31 of tag before - 
10003050h4hGIF_TAG1 - Bits 32-63 of tag before - 
10003060h4hGIF_TAG2 - Bits 64-95 of tag before - 
10003070h4hGIF_TAG3 - Bits 96-127 of tag before - 
10003080h4hGIF_CNT - Transfer status counter - 
10003090h4hGIF_P3CNT - PATH3 transfer status counter - 
100030A0h4hGIF_P3TAG - Bits 0-31 of PATH3 tag when interrupted - 
10006000h10hGIF FIFO 
DMA Controller (DMAC)
- 
100080xxhVIF0 - channel 0 - 
100090xxhVIF1 - channel 1 - 
1000A0xxhGIF - channel 2 - 
1000B0xxhIPU_FROM - channel 3 - 
1000B4xxhIPU_TO - channel 4 - 
1000C0xxhSIF0 - channel 5 - 
1000C4xxhSIF1 - channel 6 - 
1000C8xxhSIF2 - channel 7 - 
1000D0xxhSPR_FROM - channel 8 - 
1000D4xxhSPR_TO - channel 9 - 
1000E000h4hD_CTRL - DMAC control - 
1000E010h4hD_STAT - DMAC interrupt status - 
1000E020h4hD_PCR - DMAC priority control - 
1000E030h4hD_SQWC - DMAC skip quadword - 
1000E040h4hD_RBSR - DMAC ringbuffer size - 
1000E050h4hD_RBOR - DMAC ringbuffer offset - 
1000E060h4hD_STADR - DMAC stall address - 
1000F520h4hD_ENABLER - DMAC disabled status - 
1000F590h4hD_ENABLEW - DMAC disable 
Interrupt Controller (INTC)
- 
1000F000h4hINTC_STAT - Interrupt status - 
1000F010h4hINTC_MASK - Interrupt mask Subsystem Interface (SIF) - 
1000F200h4hMSCOM - EE->IOP communication - 
1000F210h4hSMCOM - IOP->EE communication - 
1000F220h4hMSFLAG - EE->IOP flags - 
1000F230h4hSMFLAG - IOP->EE flags - 
1000F240h4hControl register 
Privileged GS registers
- 
12000000h8hPMODE - various PCRTC controls - 
12000010h8hSMODE1 - 
12000020h8hSMODE2 - 
12000030h8hSRFSH - 
12000040h8hSYNCH1 - 
12000050h8hSYNCH2 - 
12000060h8hSYNCV - 
12000070h8hDISPFB1 - display buffer for output circuit 1 - 
12000080h8hDISPLAY1 - output circuit 1 control - 
12000090h8hDISPFB2 - display buffer for output circuit 2 - 
120000A0h8hDISPLAY2 - output circuit 2 control - 
120000B0h8hEXTBUF - 
120000C0h8hEXTDATA - 
120000D0h8hEXTWRITE - 
120000E0h8hBGCOLOR - background color - 
12001000h8hGS_CSR - control register - 
12001010h8hGS_IMR - GS interrupt control - 
12001040h8hBUSDIR - transfer direction - 
12001080h8hSIGLBLID - signal 
Misc registers
- 
1000F180h1hKPUTCHAR - Console output - 
1000F430h4hMCH_DRD - RDRAM initialization - 
1000F440h4hMCH_RICM 
IOP Map
Subsystem Interface (SIF)
- 
1D000000h4hMSCOM - EE->IOP communication - 
1D000010h4hSMCOM - IOP->EE communication - 
1D000020h4hMSFLAG - EE->IOP flags - 
1D000030h4hSMFLAG - IOP->EE flags - 
1D000040h4hControl register 
CDVD Drive
- 
1F402004h1hCurrent N command - 
1F402005h1hN command status (R) - 
1F402005h1hN command params (W) - 
1F402006h1hError - 
1F402007h1hSend BREAK command - 
1F402008h1hCDVD I_STAT - interrupt register - 
1F40200Ah1hDrive status - 
1F40200Fh1hDisk type - 
1F402016h1hCurrent S command - 
1F402017h1hS command status - 
1F402018h1hS command params 
Interrupt Control
- 
1F801070h4hI_STAT - Interrupt status - 
1F801074h4hI_MASK - Interrupt mask - 
1F801078h1hI_CTRL - Global interrupt disable 
DMA registers
-  
1F80108xhMDECin - channel 0 -  
1F80109xhMDECout - channel 1 -  
1F8010AxhSIF2 (GPU) - channel 2 -  
1F8010BxhCDVD - channel 3 -  
1F8010CxhSPU2 Core0 - channel 4 -  
1F8010DxhPIO - channel 5 -  
1F8010ExhOTC - channel 6 -  
1F80150xhSPU2 Core1 - channel 7 -  
1F80151xhDEV9 - channel 8 -  
1F80152xhSIF0 - channel 9 -  
1F80153xhSIF1 - channel 10 -  
1F80154xhSIO2in - channel 11 -  
1F80155xhSIO2out - channel 12 -  
1F8010F0h4hDPCR - DMA priority control -  
1F8010F4h4hDICR - DMA interrupt control -  
1F801570h4hDPCR2 - DMA priority control 2 -  
1F801574h4hDICR2 - DMA priority control 2 -  
1F801578h4hDMACEN - DMA global enable -  
1F80157Ch4hDMACINTEN - DMA global interrupt control 
IOP Timers
- 
1F80110xhTimer 0 - 
1F80111xhTimer 1 - 
1F80112xhTimer 2 - 
1F80148xhTimer 3 - 
1F80149xhTimer 4 - 
1F8014AxhTimer 5 
Serial Interface (SIO2)
- 
1F808200h40hSEND3 buffer - 
1F808240h20hSEND1/2 buffers - 
1F808260h1hIn FIFO - 
1F808264h1hOut FIFO - 
1F808268h4hSIO2 control - 
1F80826Ch4hRECV1 - 
1F808270h4hRECV2 - 
1F808274h4hRECV3 
Sound Processing Unit (SPU2)
- 
1F900000h180hCore0 Voice 0-23 registers - 
1F900190h4hKey ON 0/1 - 
1F900194h4hKey OFF 0/1 - 
1F90019Ah2hCore attributes - 
1F90019Ch4hInterrupt address H/L - 
1F9001A8h4hDMA transfer address H/L - 
1F9001ACh2hInternal transfer FIFO - 
1F9001B0h2hAutoDMA status - 
1F9001C0h120hCore0 Voice 0-23 start/loop/next addresses - 
1F900340h4hENDX 0/1 - 
1F900344h2hStatus register 
above addresses repeat for Core1 starting at 1F900400h
- 
1F900760h2hMaster Volume Left - 
1F900762h2hMaster Volume Right - 
1F900764h2hEffect Volume Left - 
1F900766h2hEffect Volume Right - 
1F900768h2hCore1 External Input Volume Left - 
1F90076Ah2hCore1 External Input Volume Right