The SDRAM controller has not been explored much and most of the information about it comes from this uboot fork:

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0x0:   - Bus error status reg 0 (CLEAR on write)
    default: 0x00000000

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0x4:   - Bus error status reg 0 (SET on write)
    default: 0x00000000

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0x8:   - Bus error status reg 1 (CLEAR on write)
    default: 0x00000000

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0xC:   - Bus error status reg 1 (SET on write)
    default: 0x00000000

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0x10:  - Bus error address reg
    default: 0x00000000

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0x11:  - Unknown         
    default: 0x00000000

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0x12:  - Unknown
    default: 0x00000000

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0x18:  - SDRAM slave interface options register
    default: 0xe0000000
    Only first 5 bits can be set. 

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0x20:  - SDRAM options register 0
    default: 0x80e00000

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0x21:  - SDRAM options register 1
    default: 0x00000000

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0x22:  - SDRAM device options
    default: 0x40000000

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0x24:  - Memory controller status register
    default: 0xa0000000

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0x30:  - Refresh timer register
    default: 0x04800000

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0x34:  - Power management idle timer register
    default: 0x07c00000

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0x38:  - PLB UABus base address
    default: 0x00000000

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0x40:  - Bank 0 config register
    default: 0x00020001

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0x44:  - Bank 1 config register
    default: 0x00000000

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0x48:  - Bank 2 config register
    default: 0x00000000

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0x48:  - Bank 3 config register
    default: 0x00000000

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0x80:  - Timing register 0
    default: 0x818d4097

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0x81:  - Timing register 1
    default: 0x40400000

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0x82:  - Clock timing register
    default: 0x40000000

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0x83:  - Write data / dm / dqs clock timing register
    default: 0x40000000

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0x84:  - Delay line control register
    default: 0x20000094 

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0x98:  - ECC error status register
    default: 0x00000000

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0x9c:
    default: 0x00000000

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0xa4: 
    default: 0x320b0000

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0xa8:
    default: 0x00003100